This technology allows high-frequency piezoelectric
A prototype was fabricated by a silicon CMOS process with a minimum line width of 65 nm, and a maximum frequency output of approximately 9 GHz was achieved with a phase fluctuation of only 180 femtoseconds. Power consumption was 12.7 mW. This performance is equivalent to a PLL Figure of Merit (FoM) of -244 dB, and it has the world's top-class performance as a fractional-N PLL. This can contribute to the realization of compact, low-cost, high-speed radio communication systems.
The study results will be announced in local time June 17 in "The 2016 Symposium on VLSI Circuits" to be held in Hawaii from June 14.
Read more at: https://phys.org/news/2016-06-nict-circuit-technology-issues-high-frequency.html#jCp